1. Field of the Invention
This invention relates to an EPROM array and in particular to an EPROM array which utilizes a virtual ground in such a manner as to substantially reduce the size of each cell in the array to make possible a much smaller integrated circuit for a given array size than heretofore possible.
2. Prior Art
Extensive efforts have been made to shrink the cell size in electrically programmable read only memories, called "EPROMS". In general, the smaller the cell size the smaller the integrated circuit die or chip containing a given number of EPROM cells and therefore the higher the yield of useful semiconductor dice in the manufacturing process. Moreover, because a smaller cell size results in a smaller integrated circuit die for a given size EPROM array, more semiconductor die can be obtained from a given sized wafer and thus the manufacturing cost per die is lower. Accordingly, efforts have been made to reduce EPROM cell size and thus the die size of a semiconductor chip containing a given size EPROM array. A general trend in the industry to improve the EPROM packing density is to apply a virtual ground architecture rather than common ground architecture to the EPROM array. The virtual ground approach eliminates much of the overhead area in the array associated with contacts and source lines. One such effort is shown, for example, in U.S. Pat. No. 4,267,632. In the '632 patent a first plurality of parallel, spaced-apart, polycrystalline silicon ("polysilicon") lines is defined on one surface of, but insulated from the silicon semiconductor substrate. Parallel, spaced apart doped regions are formed in the silicon substrate between these first polysilicon lines in alignment with these lines. A second plurality of parallel, spaced-apart, polysilicon lines insulated from the first lines and the doped regions in the substrate is formed perpendicular to the first lines and the doped regions. The second lines are then used as an etch mask to remove those portions of the first lines not covered by the second lines. The portions of the first lines remaining beneath the second lines are located between the doped regions and are the floating gates of the EPROM transistors. While the '632 patent yields a plurality of floating gate devices in a relatively high density array, the cell size is still larger than desired. One reason for this is that one metal line is formed above each elongated doped region in the silicon substrate. Consequently, the size of the array is increased both by the widths of these metal lines and by the need to have numerous contacts (which of necessity are wider than the widths of the metal lines) between such metal lines and the underlying elongated, parallel, spaced-apart doped regions. Having a symmetrical transistor (source and drain are interchangeable) complicates the programming function in virtual ground arrays. To compensate for this complication a much more complicated Y-decoder is required. This complicated Y-decoder increases the chip size. Moreover, due to the drain turn-on problem (coupling of drain voltage into the floating gate and making the EPROM cell leak current even when V.sub.G =0), the EPROM cell has a longer channel length than the minimum channel length possible using the technology. This in turn increases cell size and compromises the cell performance.
To resolve some of the above problems a split gate non-volatile EPROM array is disclosed in U.S. Pat. No. 4,639,893 issued Jan. 27, 1987 on an application of Eitan filed May 15, 1984. In Eitan's invention a memory cell contains both a control gate and a floating gate. The floating gate is self-aligned to the drain region but the control gate is not self-aligned. Eitan teaches that the portion of the transistor channel length beneath the floating gate is defined by the floating gate itself regardless of any processing misalignments thereby insuring a constant channel length under the floating gate. This is achieved by using the floating gate to define one edge of the drain region (i.e. to self-align one edge of the drain to one edge of the floating gate). In the process disclosed by Eitan to make the self-aligned split gate structure, the source region is defined at the same time as the drain region but the alignment of the source region relative to the floating gate is not critical so long as the source region does not underlie and is spaced from the floating gate.
Eitan's split gate transistor thus achieves a channel region beneath the floating gate with a precisely defined length independent of manufacturing tolerances and a remaining relatively imprecisely defined channel region beneath a control gate electrode (which is part of the word line) between the floating gate and the source region.
An advantage of the Eitan structure is that any misalignment between the floating gate and the source region is covered by the control gate and has little effect on the operation of the memory cell while at the same time the floating gate is self-aligned to the drain region.
The asymmetrical split gate cell of Eitan described above overcomes the program disturb as well as the drain turn on associated with the symmetrical EPROM cell in the above-described virtual ground array.
The split gate structure of the '893 patent requires a pair of transistors in each cell: a floating gate transistor for use in storing a bit of information and a control transistor. Both the floating gate and the control transistors are in series between the source and drain of the composite structure. The control transistor takes space and thus increases cell size relative to the size of a cell with just a floating gate transistor.
In the '632 patent a metal line must be formed over every diffusion bit-line to contact the diffusion bit-line at selected places along its length. Due to the small number of contacts (one every 32 cells or one every 64 cells) the metal pitch with contact can be packed better by staggering the contacts. However, the cell pitch is still limited by the metal pitch which is always wider than the minimum design rule possible due to lithography only.
There are two ways to increase the density of EPROMS. One way is to reduce and shrink design rules. The other way is to come up with architectural improvements. FIG. 1 shows that the density of EPROMS has doubled just about every 1.8 years. FIG. 2 shows that cell size (in area dimensions) did not decrease at the same rate and only halved every 3.5 years. As a result, the EPROM chip size has increased dramatically from 170 mils square for a 256 k EPROM around 1981 to 360 to 380 mils square for a 4 megabit EPROM in 1989. FIG. 2 shows that the theoretical minimum cell size is about 2.5 to 3 times smaller than the standard cell size with the same design rules. Minimum theoretical cell size shown in FIG. 2 is related to a minimum feature size. Traditionally the minimum feature size corresponds to the minimum width of a line and the minimum spacing between two such lines. Theoretically if 0.8 micron is the minimum width for a polycrystalline silicon line and 0.8 micron is the minimum pitch between two polycrystalline silicon lines, then a square 1.6 microns on a side is possible. Typically when one defines a minimum feature size for a technology it will be the polycrystalline silicon which actually has the minimum feature size. Furthermore, typically the minimum diffusion is 1.3 to 1.5 times larger than the minimum feature size of the polycrystalline silicon while the metal plus contact is 1.5 to 2.0 times larger than the minimum feature size. To approach the theoretical minimum size with an EPROM cell, one has to define a cell which is "poly pitch limited" i.e., which has its minimum features defined by the polycrystalline silicon rather than by the diffusion or the metal and contact dimensions.
FIG. 3 illustrates the prior art standard EPROM layout in top view. The critical design rules involve the Y-pitch (taken along the X axis) which consists of the metal plus the contact pitch and the X-pitch (taken along the Y axis) which reflects half a shared drain contact, the distance from the drain contact to the double poly, the minimum poly pitch and half a diffusion pitch for the shared source line. In a 0.8 micron technology, the cell size will be around 7.5 microns square.
FIG. 4 illustrates the layout of a prior art symmetrical virtual ground EPROM. In FIG. 4 the critical design rules along the Y-pitch (along the X axis) are the metal plus the contact while the critical X-pitch design rules (along the Y axis) are poly pitch limited. The symmetrical virtual ground approach shown in the plan view of the structure of FIG. 4 requires a complex write cycle which needs a lot of peripheral overhead circuitry. Overall, therefore, the reduced cell size taken together with the peripheral complexity yields no substantial improvement in the die size.
The asymmetrical virtual ground structure of the type used by Wafer Scale Integration (see FIGS. 5a and 5b and the '893 patent), the assignee of this application, has in the Y-pitch (along the X axis) metal plus one-half a contact and has in the X-pitch (along the Y axis) a diffusion pitch limitation. As shown in FIGS. 5a and 5b, the cell is asymmetrical. This yields a very simple peripheral circuit and thus yields the smallest die size with the least aggressive design rules and the simplest peripheral circuitry. For the same 0.8 micron technology, this cell size will be about 4.5 microns square.
Therefore the architectural improvement which reduces cell size to the minimum feature cell size is the preferred approach to take in reducing the size (i.e., "scaling") EPROMS.